The invention relates to random access memory (RAM), and in particular high density RAMs implemented as integrated circuit semiconductor devices.
Random access memories utilizing junction field effect transistors (JFETs) are known from the International Solid-State Circuits Conference (ISSCC) proceedings, February 1973, pages 34 et seq. The memory cell implementation described in that paper utilizes a JFET in series with a threshold diode, and having three address lines in each cell. The three address lines are a word line, a bit line, and a read line. Such an implementation is an improvement compared with previous RAMs which required four address lines for each cell.
Another implementation of a JFET RAM is described in the IEEE JSSC, August 1976, pages 519. Here again each cell of the memory matrix has three address lines, however the threshold diodes found in the previously discussed implementation have been omitted.
Furthermore, a photo matrix sensor implemented using JFETs is also known. Each of the sensor cells is specified or selected by means of a matrix of word lines and bit lines, and information from the addressed sensor cell is read out indicating the conductivity of the JFET channel existing between a main electrode of the JFET connected to a bit line and the substrate of the semiconductor body in which the sensor is implemented. In such arrangement, each bit line is supplied with a fixed voltage through its own discrete load resistor. Writing information in the sensor cells is achieved by exposing the sensor to the pattern of light and shadow, which represent information. The surface area of cells used in such photo sensors is relatively large, since it is important that the conductor tracks for selecting the memory cells avoid intercepting the light reaching the cells. Such a configuration while uniquely suitable for photo sensors cannot however be used in a high density RAM.